This invention relates generally to semiconductor technology and more particularly to the formation of silicided electrodes in active semiconductor devices, such as MOS transistors.
An important subject of ongoing research in the semiconductor industry is the reduction in the dimensions of devices used in integrated circuits. Planar transistors such as metal oxide semiconductor (MOS) transistors are particularly suited to use in high density integrated circuits. As the size of MOS transistors and other active devices decreases, the dimensions of the source/drain/gate electrodes, and the channel region of each device, decrease correspondingly.
The design of ever smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junction regions. Shallow junctions are necessary to avoid lateral diffusion of implantation dopants into the channel, such diffusion being undesirable because it contributes to leakage currents and poor breakdown performance. Shallow source/drain junction regions, for example, less than 1000 angstroms (.ANG.) thick, and preferably less than 500 .ANG. thick, are necessary for acceptable performance in short channel devices.
When shallow junction electrodes are used in transistors, it becomes more difficult to provide reliable, low resistance connections to the source/drain regions of the device. Metal-silicide contacts are a typical means of effecting such connections to source/drain/gate electrodes. In such contacts, conductive metal is deposited on the silicon electrodes and annealed to form a metal-silicon compound on the surface of the electrodes. The compound, called silicide, is electrically and physically bonded to the electrode, and has a substantially lower sheet resistance than the doped silicon on which it is formed. An important advantage of silicide contacts in small devices is that suicide is only formed where the deposited metal is in contact with silicon. By means of a selective etch the metal is readily removed from the non-silicided areas. Thus, the silicide regions are automatically aligned on the electrode surfaces only. This self-aligned silicide process is generally referred to as the "salicide" process.
One difficulty presented by the salicide process on shallow junction source and drain regions is that it consumes a portion of the surface silicon. The metal-silicide is formed from a chemical reaction which occurs during an annealing step, when the deposited metal reacts with the underlying silicon. Electrodes with very thin junction depths have less silicon to sacrifice to the formation of silicide, and can only permit a very thin layer of silicide to be formed. Thin silicide films are known to be thermally unstable and have an undesirably high sheet resistance.
One prior art technique for increasing the thickness of the silicide contacts is to deposit additional silicon on the surface of the source and drain regions. The additional silicon in the raised source and drain electrodes can then be used in the reaction with deposited metal to form thicker silicide layers. This solution has disadvantages because the deposition of additional silicon produces additional diffusion of dopants and additional process steps which increase fabrication costs.
It is a well observed fact that inconsistent junction leakage currents often result from the salicidation of source/drain electrodes. It is believed that the random leakage phenomena is the result of silicide edges. The formation of "excess" suicide, into the source/drain areas around the edges of the source/drain electrodes, and in close proximity to the junction areas underlying the source/drain electrodes, leads to the leakage current problem. These incursions, perturbations, or greater thicknesses of silicide cause large electric field variances, and may even permit electrical conductivity extending through the junctions. While the amount of silicide formed on the main body of the source/drain electrodes is controlled by the thickness of the deposited silicidation metal, additional supplies of the metal are available around the edges of the source/drain electrodes where the metal is deposited on non-reacting surfaces, such as oxides.
A co-pending patent application entitled PARTIAL SILICIDATION METHOD TO FORM SHALLOW SOURCE/DRAIN ELECTRODES, invented by Maa et al., filed on Feb. 13, 1998, and assigned to the same assignees as the instant patent application, presents one solution to the problem of silicided edges. In the above-mentioned application, the silicide layer on the source/drain electrodes is formed in a two-step anneal process. A low temperature anneal begins the silicidation process. Then, the unreacted silicidation metal is removed and a higher temperature anneal finishes the process. Removing the unreacted metal between annealings prevents the formation of excessive silicide around the edges of the source/drain electrodes. However, multiple annealing steps are not convenient for all processes.
Accordingly, a method for forming shallow source/drain junctions with low leakage currents in a MOS transistor is provided. The method comprises the steps of:
a) forming source/drain regions, having a horizontal top surface and edges around the perimeter of the top surface bounded by field oxide regions in a silicon well, and forming a gate electrode with vertical sidewalls adjacent the top surface; PA1 b) selectively forming nitride overhang structures on the field region adjoining the source/drain top surfaces and the vertical sidewalls of the gate electrode, creating a gap between nitride structures and the edges of the top surfaces, whereby the perimeter of the top surfaces is located in the gap; PA1 c) depositing metal overlying the top surfaces, gate electrode, and field oxide in a thin enough layer so as to form gaps between the nitride structures and the source/drain top surfaces, isolating the metal overlying the top surfaces from the metal overlying the field oxide and the gate electrode; and PA1 d) annealing the metal at a first temperature and first time duration, forming a layer of low resistance silicide compound having a predetermined nominal silicide layer thickness and a predetermined silicide thickness tolerance, whereby silicide is formed on the source/drain top surfaces, but not the insulating surfaces adjoining the source and drain. PA1 a.sub.1) depositing a thin layer of oxide overlying the gate electrode, source/drain regions, and field oxide regions; PA1 a.sub.2) depositing a nitride layer overlying the oxide layer deposited in Step a.sub.1); PA1 a.sub.3) forming a photoresist mask selectively overlying the field oxide regions, exposing the nitride layer overlying the source/drain top surfaces and gate electrode, whereby the field oxide is protected; PA1 a.sub.4) anisotropically etching, in the vertical direction, the nitride layer, removing the nitride layer overlying the source/drain top surface and exposing the oxide layer deposited in Step a.sub.1), but not etching the nitride overlying the vertical sidewalls of the gate electrode; PA1 a.sub.5) etching to remove the photoresist overlying the field oxide region. Then, Step b) includes isotropically etching with an etchant having a higher oxide to nitride etch selectivity, removing the oxide layer overlying the source/drain regions, to form the nitride overhang structures. PA1 a.sub.6) implanting the source/drain regions with dopant and annealing, forming source/drain junction areas with metallurgical edges at a junction depth in the range between 300 and 2000 .ANG. from the source/drain top surfaces. Alternately, a further step, follows Step d), of: PA1 e) implanting the source/drain regions with dopant and annealing, forming source/drain junction areas with metallurgical edges at a junction depth of between 300 and 2000 .ANG..
The nitride overhang structure is created by the following method:
The source/drain junction areas are completely formed either before, or after the silicidation process. One aspect of the invention includes a further step, following Step a), and preceding Step a.sub.1), of:
A MOS transistor, and process to make a transistor having shallow source/drain junctions with low leakage current are also provided. The transistor comprises silicon source/drain regions having horizontal top surfaces, and edges around the perimeter of said top surfaces. The transistor also comprises field oxide regions with boundaries adjacent at least part of the top surface perimeter. Source/drain junction areas exist with metallurgical edges at a predetermined junction depth from the respective source/drain top surfaces. A gate electrode having vertical sidewalls is located adjacent the source/drain regions. Nitride overhang structures temporarily overlie the gate electrode vertical sidewalls and field oxide boundaries, adjoining the source/drain top surfaces. The nitride overhang structures have a first gap between the overhang structures and the source/drain top surfaces. Finally, a low resistance silicide layers overlies the source/drain top surfaces. The sulicide layers have a predetermined nominal silicide layer thickness and a predetermined silicide thickness tolerance, whereby the spacing between the junction area and said silicide layer is maximized by preventing silicide perturbations on said silicon top surfaces. The nitride structures and silicide layers are formed per the above-described method. After silicidation, the nitride structures can be removed.